In this paper we present an algorithm for allocating scan flops to scan chains based on the placement information of flops. The objective of the algorithm is to reduce the scan wire length, the number of level shifters and the number of lockup latches in the scan path. The algorithm uses a novel partitioning based approach to allocate and order the scan flops for a particular scan chain. The scan flops are allo- cated to a number of partitions. These partitions are then ordered for the scan chains based on the physical location of the scan-in and scan-out pins of the scan chain and the aspect ratio of the layout. To the best of our knowledge this is the first algorithm that explicitly attempts to reduce the number of level shifters in the scan data path. Exper- imental results obtained for some industrial circuits show that the number of level shifters in the scan data path is halved for some industrial test cases over approaches that are not multiple supply voltage aware. Scan wire lengths too are reduced by up to 45% over previous approaches for the above designs. Additionally we obtain upto 90% scan wire length reductions over previous approaches [4],[11] for some ISCAS-89 benchmark circuits.