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21st International Conference on VLSI Design (VLSI Design 2008)
Testing Flash Memories for Tunnel Oxide Defects
Hyderabad, India
January 04-January 08
ISBN: 0-7695-3083-4
ASCII Text
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Mohammad Gh. Mohammad, Kewal K. Saluja, "Testing Flash Memories for Tunnel Oxide Defects," VLSI Design, International Conference on, pp. 157-162, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.41,
author = {Mohammad Gh. Mohammad and Kewal K. Saluja},
title = {Testing Flash Memories for Tunnel Oxide Defects},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {157-162},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.41},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Testing Flash Memories for Tunnel Oxide Defects
SN - 1063-9667
SP157
EP162
A1 - Mohammad Gh. Mohammad,
A1 - Kewal K. Saluja,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
defects is one of the most important aspects to guarantee cell reliability. Defective tunnel oxide layer in core memory cells can result in various disturb faults. In this paper, we study various defects in the insulating layers of a 1T flash cell and analyze their impact on cell performance. Further, we present a test methodology and test algorithms that enable the detection of tunnel oxide defects in an efficient manner.
Citation:
Mohammad Gh. Mohammad, Kewal K. Saluja, "Testing Flash Memories for Tunnel Oxide Defects," vlsid, pp.157-162, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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