VLSI Implementation of a Digitally Tunable G<sub>m</sub>-C Filter with Double CMOS Pair

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VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - VLSI Implementation of a Digitally Tunable G<sub>m</sub>-C Filter with Double CMOS Pair

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21st International Conference on VLSI Design (VLSI Design 2008)

VLSI Implementation of a Digitally Tunable G_m-C Filter with Double CMOS Pair

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	S. Ramasamy, B. Venkataramani, K. Anbugeetha, "VLSI Implementation of a Digitally Tunable G<sub>m</sub>-C Filter with Double CMOS Pair," VLSI Design, International Conference on, pp. 317-322, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.39, author = {S. Ramasamy and B. Venkataramani and K. Anbugeetha}, title = {VLSI Implementation of a Digitally Tunable G<sub>m</sub>-C Filter with Double CMOS Pair}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {317-322}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - VLSI Implementation of a Digitally Tunable G<sub>m</sub>-C Filter with Double CMOS Pair SN - 1063-9667 SP317 EP322 A1 - S. Ramasamy, A1 - B. Venkataramani, A1 - K. Anbugeetha, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

S. Ramasamy

B. Venkataramani

K. Anbugeetha

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.39

This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of Gm-C filters . The advantage of this scheme is that, instead of varying the power supply, the bias voltages at high impedance nodes are varied for frequency (F) tuning. A current steering DAC is proposed for controlling these bias voltages. Another major contribution of this paper is the use of switchable transconductance cell for Q-tuning. This dispenses with the need for two separate biasing circuits (for F and Q tuning). To study the performance of proposed schemes, a bandpass filter is implemented on TSMC-0.18?m CMOS process using Gm/Id design methodology. The simulation results show a good centre frequency (10MHz -120MHz) and pass band (10MHz -80MHz) tuning. The proposed approach guarantees the upper bound on THD to be -40dB for 1 Vpp signal swing. The use of inverters with double CMOS pair results in 21dB higher PSRR compared to those using push pull inverter.

Citation:

S. Ramasamy, B. Venkataramani, K. Anbugeetha, "VLSI Implementation of a Digitally Tunable G_m-C Filter with Double CMOS Pair," vlsid, pp.317-322, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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