Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

V
VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

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	Similar Articles Articles by Yuanlin Lu Articles by Vishwani D. Agrawal

21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Yuanlin Lu, Vishwani D. Agrawal, "Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation," VLSI Design, International Conference on, pp. 527-532, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.29, author = {Yuanlin Lu and Vishwani D. Agrawal}, title = {Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {527-532}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.29}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation SN - 1063-9667 SP527 EP532 A1 - Yuanlin Lu, A1 - Vishwani D. Agrawal, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Yuanlin Lu

Vishwani D. Agrawal

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.29

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation.

Citation:

Yuanlin Lu, Vishwani D. Agrawal, "Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation," vlsid, pp.527-532, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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