21st International Conference on VLSI Design (VLSI Design 2008) An Acceleration and Optimization Method for Optical Reconfiguration Hyderabad, India January 04-January 08 ISBN: 0-7695-3083-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.26
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holo- graphic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic mem- ory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to real- ize a short reconfiguration time in ORGAs is to im- plement a high-power laser array. However, such an array presents the disadvantages of high power con- sumption, large implementation space, high cost, and so on. Therefore, this paper presents an accelera- tion method to increase ORGAs' reconfiguration fre- quency without the necessity for any increase of laser power. This technique also includes optimization be- tween the number of reconfiguration contexts and the reconfiguration frequency. The description in this pa- per clarifies the advantages using simulation and ex- perimental results.
Citation:
Minoru Watanabe, Naoki Yamaguchi, "An Acceleration and Optimization Method for Optical Reconfiguration," vlsid, pp.607-612, 21st International Conference on VLSI Design (VLSI Design 2008), 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||