quently used datapath operation in modern integrated circuit designs, especially in Digital Signal Processing (DSP) and Graph- ics applications. Since POS blocks typically incur a significant amount of delay, these blocks often become critical in determining the performance of the entire chip. Hence, to improve the efficiency of this operation, it is desirable to use an architecture with good performance characteristics. This paper presents an architectural optimization approach to synthesize a faster POS block, which can be very useful in reducing the delay of the design without significantly impacting its area. Our architecture for the Product-of-Sum (POS) block is primarily based on the analysis of the corresponding Sum-of-Products (SOP) expression or a hybrid combination of the POS and the SOP expressions. In our technique, we extensively use arrival-times of the input signals of the Product-of-Sum block to determine the suitable architecture of the block. We have tested our approach using a variety of POS blocks implemented under varying timing constraints and technology libraries. Experimental results demonstrate that our proposed solution is 10.92% faster (and 3.54% larger) than the corresponding block generated by a commercially available best-in-class datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.