and Graphics applications, the arithmetic Sum-of-Product (SOP) is an important and computationally intensive operation, con- suming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power- efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective- inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller ( 8.59% on average) and marginally faster ( 0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power ( 7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.