Design-for-testability (DFT) approaches that allow a synchronous sequential circuit to enter states that it can- not enter during functional operation improve the fault coverage achievable for the circuit. However, non- functional operation during test application may result in switching activity that is significantly higher than under functional operation. This may lead to unnecessary yield loss due to supply voltage droops that slow the circuit but will not occur during functional operation. To address this issue we describe a DFT approach and a test generation procedure that improve the fault coverage by slowing down the state transitions of certain state variables rela- tive to others. Unlike approaches that are based on hold- ing values of state variables stable for unlimited numbers of clock cycles, the proposed approach resumes functional operation every limited number of clock cycles. This is shown to result in maximum switching activity that is in most cases lower than that obtained under the application of a functional test sequence, and never needs to exceed it.