As on-chip interconnect in deep-submicron designs con- tribute to the system-wide power consumption, minimiza- tion of interconnect power consumption has become one of the important design issues in deep-submicron technolo- gies. As transition activity mainly determines the intercon- nect power consumption, several bus encoding techniques have been proposed to minimize the activity. Unlike the existing low-power or energy-efficient bus encoding techniques, in this paper, we propose a scheme which exploits both dynamic voltage scaling and variable cycle transmission mechanisms for minimizing on-chip in- terconnect energy consumption. We transmit data using variable cycle transmission method and, based on the de- lay savings achieved through variable cycle transmission method at regular intervals, scale the voltage and frequency to obtain significant energy savings. Using our technique for a 5mm interconnect wire we achieved energy savings of 30% and 45% over the base case in the address bus and data bus, respectively. Our technique also reduces the energy-delay-product by 34% and 52% for address bus and data bus, respectively.