Architecture Exploration for Low Power Design

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21st International Conference on VLSI Design (VLSI Design 2008)

Architecture Exploration for Low Power Design (PDF)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Vinod Kathail, Tom Miller, "Architecture Exploration for Low Power Design," VLSI Design, International Conference on, pp. 10-11, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.132, author = {Vinod Kathail and Tom Miller}, title = {Architecture Exploration for Low Power Design}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {10-11}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.132}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Architecture Exploration for Low Power Design SN - 1063-9667 SP10 EP11 A1 - Vinod Kathail, A1 - Tom Miller, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

Vinod Kathail

Tom Miller

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.132

Increasingly SoC design is driven by integrated mobile devices such as cell phones, music players and hand-held game consoles. These devices rely on standard algorithms such as H.264, 802.11n, or JPEG2000, which allow room for innovative implementations that can result in differentiated products. Designers of these devices are constantly on a tread-mill to integrate more and more features within tight time-to-market constraints. They also play a very delicate balancing act to meet the aggressive goals for power, area and performance.

Citation:

Vinod Kathail, Tom Miller, "Architecture Exploration for Low Power Design," vlsid, pp.10-11, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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