A new jitter reduction circuit is proposed for reducing the timing jitter in a serializer-deserializer (SERDES). In- stead of using elaborate hardware to calculate the jitter, we use the jittered signal's autocorrelation to remove the jitter. The motivation for this work was to provide a re- duced jitter phase-locked loop (PLL), so that incorporat- ing a built-in self-testing (BIST) mechanism for PLL's and SERDES would be simplified. The technique involves trans- mit and receive side jitter reducer pulse shaping circuits made of only 14 and 20 transistors, respectively. They re- duce the jitter in the clock generated by the PLL at the transmit side, and the jitter between the recovered clock and the serial data at the receive side. The jitter reducers are designed in 70 nm Berkeley Predictive process models and tested with various types of input jitter. In the case of the transmit side, the peak-to-peak random jitter (RJ) is re- duced, on average, by 45.51% and also the average trans- mit and receive side RMS jitter is reduced, on average, by 62.24% and 35.88%, respectively. The bit-error rate (BER) of the SERDES computed probabilistically is improved from 8.3 ? 10-2 to 6.44 ? 10-20, for input RMS periodic jitter (PJ) of 71.77 ps. The BER for the PCI express bus must be 1 ? 10-12.