Compact Modeling of Suspended Gate FET

V
VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - Compact Modeling of Suspended Gate FET

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Yogesh Singh Chauhan Articles by D. Tsamados Articles by N. Abel? Articles by C. Eggimann Articles by M. Declercq Articles by A.M. Ionescu

21st International Conference on VLSI Design (VLSI Design 2008)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Yogesh Singh Chauhan, D. Tsamados, N. Abel?, C. Eggimann, M. Declercq, A.M. Ionescu, "Compact Modeling of Suspended Gate FET," VLSI Design, International Conference on, pp. 119-124, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.11, author = {Yogesh Singh Chauhan and D. Tsamados and N. Abel? and C. Eggimann and M. Declercq and A.M. Ionescu}, title = {Compact Modeling of Suspended Gate FET}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {119-124}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Compact Modeling of Suspended Gate FET SN - 1063-9667 SP119 EP124 A1 - Yogesh Singh Chauhan, A1 - D. Tsamados, A1 - N. Abel?, A1 - C. Eggimann, A1 - M. Declercq, A1 - A.M. Ionescu, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.11

Suspended Gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysics and ISE-DESSIS in a self-consistent system is developed. The model is then validated on this numerical device simulation of SGFET. The model shows excellent performance over the entire drain and gate voltage range. The model has been implemented in Verilog-A code and tested on ELDO and Spectre simulators, which makes it useful for circuit simulations using SGFET devices.

Citation:

Yogesh Singh Chauhan, D. Tsamados, N. Abel?, C. Eggimann, M. Declercq, A.M. Ionescu, "Compact Modeling of Suspended Gate FET," vlsid, pp.119-124, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.