Single Error Correcting Finite Field Multipliers Over GF(2m)

V
VLSID
2008
21st International Conference on VLSI Design (VLSI Design 2008)
Abstract - Single Error Correcting Finite Field Multipliers Over GF(2m)

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21st International Conference on VLSI Design (VLSI Design 2008)

Single Error Correcting Finite Field Multipliers Over GF(2^m)

Hyderabad, India

January 04-January 08

ISBN: 0-7695-3083-4

	ASCII Text	x
	Jimson Mathew, A. Costas, A.M. Jabir, H. Rahaman, D.K. Pradhan, "Single Error Correcting Finite Field Multipliers Over GF(2<i><sup>m</sup></i>)," VLSI Design, International Conference on, pp. 33-38, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.

	BibTex	x
	@article{ 10.1109/VLSI.2008.105, author = {Jimson Mathew and A. Costas and A.M. Jabir and H. Rahaman and D.K. Pradhan}, title = {Single Error Correcting Finite Field Multipliers Over GF(2<i><sup>m</sup></i>)}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2008}, issn = {1063-9667}, pages = {33-38}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Single Error Correcting Finite Field Multipliers Over GF(2<i><sup>m</sup></i>) SN - 1063-9667 SP33 EP38 A1 - Jimson Mathew, A1 - A. Costas, A1 - A.M. Jabir, A1 - H. Rahaman, A1 - D.K. Pradhan, PY - 2008 VL - 0 JA - VLSI Design, International Conference on ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.105

designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity prediction circuitry. Area, power and delay overhead for the proposed design technique is analyzed. It is found that compared to the traditional Triple Modular Redundancy (TMR) techniques for single error correction the proposed technique is very cost efficient. Index Terms: Error Correcting Codes, Galois Field Multiplier, Cryptography, VLSI.

Citation:

Jimson Mathew, A. Costas, A.M. Jabir, H. Rahaman, D.K. Pradhan, "Single Error Correcting Finite Field Multipliers Over GF(2^m)," vlsid, pp.33-38, 21st International Conference on VLSI Design (VLSI Design 2008), 2008

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