Hybrid Multisite Testing at Manufacturing

I
ITC
2003
International Test Conference 2003 (ITC'03)
Abstract - Hybrid Multisite Testing at Manufacturing

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International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	H. Hashempour, F. J. Meyer, F. Lombardi, F. Karimi, "Hybrid Multisite Testing at Manufacturing," Test Conference, International, pp. 927, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1271079, author = {H. Hashempour and F. J. Meyer and F. Lombardi and F. Karimi}, title = {Hybrid Multisite Testing at Manufacturing}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {927}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1271079}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Hybrid Multisite Testing at Manufacturing SN - 1089-3539 SP EP A1 - H. Hashempour, A1 - F. J. Meyer, A1 - F. Lombardi, A1 - F. Karimi, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

H. Hashempour, Northeastern University, Boston, Mass

F. J. Meyer, Northeastern University, Boston, Mass

F. Lombardi, Northeastern University, Boston, Mass

F. Karimi, LTX Corp., San Jose, CA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1271079

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.

Citation:

H. Hashempour, F. J. Meyer, F. Lombardi, F. Karimi, "Hybrid Multisite Testing at Manufacturing," itc, pp.927, International Test Conference 2003 (ITC'03), 2003

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