CMOS Built-In Test Architecture for High-Speed Jitter Measurement

I
ITC
2003
International Test Conference 2003 (ITC'03)
Abstract - CMOS Built-In Test Architecture for High-Speed Jitter Measurement

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International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz, "CMOS Built-In Test Architecture for High-Speed Jitter Measurement," Test Conference, International, pp. 67, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1270826, author = {Henry C. Lin and Karen Taylor and Alan Chong and Eddie Chan and Mani Soma and Hosam Haggag and Jeff Huard and Jim Braatz}, title = {CMOS Built-In Test Architecture for High-Speed Jitter Measurement}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {67}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270826}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - CMOS Built-In Test Architecture for High-Speed Jitter Measurement SN - 1089-3539 SP EP A1 - Henry C. Lin, A1 - Karen Taylor, A1 - Alan Chong, A1 - Eddie Chan, A1 - Mani Soma, A1 - Hosam Haggag, A1 - Jeff Huard, A1 - Jim Braatz, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

Henry C. Lin, University of Washington, Seattle, WA

Karen Taylor, University of Washington, Seattle, WA

Alan Chong, University of Washington, Seattle, WA

Eddie Chan, University of Washington, Seattle, WA

Mani Soma, University of Washington, Seattle, WA

Hosam Haggag, Santa Clara Design Center, National Semiconductor, Santa Clara, CA

Jeff Huard, Tacoma Design Center, National Semiconductor, Federal Way, WA

Jim Braatz, Tacoma Design Center, National Semiconductor, Federal Way, WA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270826

A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution of 70ps RMS jitter occupying 0.0575mm² area.

Citation:

Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz, "CMOS Built-In Test Architecture for High-Speed Jitter Measurement," itc, pp.67, International Test Conference 2003 (ITC'03), 2003

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