Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories

I
ITC
2003
International Test Conference 2003 (ITC'03)
Abstract - Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories

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International Test Conference 2003 (ITC'03)

Charlotte, NC, USA

September 30-October 02

ISBN: 0-7803-8107-6

	ASCII Text	x
	Derek Wright, Manoj Sachdev, "Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories," Test Conference, International, pp. 39, International Test Conference 2003 (ITC'03), 2003.

	BibTex	x
	@article{ 10.1109/TEST.2003.1270823, author = {Derek Wright and Manoj Sachdev}, title = {Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories}, journal ={Test Conference, International}, volume = {0}, year = {2003}, issn = {1089-3539}, pages = {39}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270823}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories SN - 1089-3539 SP EP A1 - Derek Wright, A1 - Manoj Sachdev, PY - 2003 KW - null VL - 0 JA - Test Conference, International ER -

Derek Wright, University of Waterloo, Canada

Manoj Sachdev, University of Waterloo, Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270823

Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this paper, we carried out a transistor-level fault analysis and devise a search path test algorithm. The proposed algorithm is of the order (nl / log₂n) compared to the brute-force algorithm of complexity (nl). For the analyzed CAM, the search path test complexity is reduced by 30x.

Citation:

Derek Wright, Manoj Sachdev, "Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories," itc, pp.39, International Test Conference 2003 (ITC'03), 2003

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