Core-Based Scan Architecture for Silicon Debug

I
ITC
2002
International Test Conference 2002 (ITC'02)
Abstract - Core-Based Scan Architecture for Silicon Debug

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International Test Conference 2002 (ITC'02)

Baltimore, MD, USA

October 07-October 10

ISBN: 0-7803-7543-2

	ASCII Text	x
	Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel, "Core-Based Scan Architecture for Silicon Debug," Test Conference, International, pp. 638, International Test Conference 2002 (ITC'02), 2002.

	BibTex	x
	@article{ 10.1109/TEST.2002.1041815, author = {Bart Vermeulen and Tom Waayers and Sandeep Kumar Goel}, title = {Core-Based Scan Architecture for Silicon Debug}, journal ={Test Conference, International}, volume = {0}, year = {2002}, isbn = {0-7803-7543-2}, pages = {638}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041815}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Core-Based Scan Architecture for Silicon Debug SN - 0-7803-7543-2 SP EP A1 - Bart Vermeulen, A1 - Tom Waayers, A1 - Sandeep Kumar Goel, PY - 2002 KW - null VL - 0 JA - Test Conference, International ER -

Bart Vermeulen, Philips Research Laboratories

Tom Waayers, Philips Research Laboratories

Sandeep Kumar Goel, Philips Research Laboratories

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041815

In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.

Citation:

Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel, "Core-Based Scan Architecture for Silicon Debug," itc, pp.638, International Test Conference 2002 (ITC'02), 2002

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