Integration of SRAM Redundancy into Production Test

I
ITC
2002
International Test Conference 2002 (ITC'02)
Abstract - Integration of SRAM Redundancy into Production Test

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International Test Conference 2002 (ITC'02)

Baltimore, MD, USA

October 07-October 10

ISBN: 0-7803-7543-2

	ASCII Text	x
	Jayasanker Jayabalan, Juraj Povazanec, "Integration of SRAM Redundancy into Production Test," Test Conference, International, pp. 187, International Test Conference 2002 (ITC'02), 2002.

	BibTex	x
	@article{ 10.1109/TEST.2002.1041760, author = {Jayasanker Jayabalan and Juraj Povazanec}, title = {Integration of SRAM Redundancy into Production Test}, journal ={Test Conference, International}, volume = {0}, year = {2002}, isbn = {0-7803-7543-2}, pages = {187}, doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041760}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Integration of SRAM Redundancy into Production Test SN - 0-7803-7543-2 SP EP A1 - Jayasanker Jayabalan, A1 - Juraj Povazanec, PY - 2002 KW - null VL - 0 JA - Test Conference, International ER -

Jayasanker Jayabalan, Infineon Technologies Asia Pacific Pte Ltd

Juraj Povazanec, Infineon Technologies Asia Pacific Pte Ltd

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041760

In this paper, we present the implementation of a multiple-SRAM redundancy concept, which increase the yield of a 100 mm2, 0.18 micron technology device with a total memory size of 3 Mbits, by the factor of 20%. A number of test and design considerations are detailed.

Citation:

Jayasanker Jayabalan, Juraj Povazanec, "Integration of SRAM Redundancy into Production Test," itc, pp.187, International Test Conference 2002 (ITC'02), 2002

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