International Test Conference 2002 (ITC'02) An Embedded Core for Sub-Picosecond Timing Measurements Baltimore, MD, USA October 07-October 10 ISBN: 0-7803-7543-2
The continued market demand for GHz processors and high-capacity communication systems results in an increasing number of low-cost high volume ICs with multi-GHz clocks and/or multi-Gb/s serial communication interfaces. For such devices, timing specifications, e.g., jitter and skew, in the range of few picoseconds (RMS and/or p-p) are common. We describe an embedded core that allows such measurements. The core is small, functionally non-intrusive, and easily scalable for testing multiple circuits and signals on the chip. To reach the required sub-picosecond accuracy, we present a novel measurement and data processing technique, based on noise scaling. The core has a standard low-speed serial interface.
Citation:
Sassan Tabatabaei, Andr? Ivanov, "An Embedded Core for Sub-Picosecond Timing Measurements," itc, pp.129, International Test Conference 2002 (ITC'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||