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Early Analysis of Fault-based Attack Effects in Secure Circuits
October 2007 (vol. 56 no. 10)
pp. 1431-1434
ASCII Text
x 
 
R. Leveugle, "Early Analysis of Fault-based Attack Effects in Secure Circuits," IEEE Transactions on Computers, vol. 56, no. 10, pp. 1431-1434, October, 2007.
 
 
BibTex
x
 
@article{ 10.1109/TC.2007.1078,
author = {R. Leveugle},
title = {Early Analysis of Fault-based Attack Effects in Secure Circuits},
journal ={IEEE Transactions on Computers},
volume = {56},
number = {10},
issn = {0018-9340},
year = {2007},
pages = {1431-1434},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.1078},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Early Analysis of Fault-based Attack Effects in Secure Circuits
IS - 10
SN - 0018-9340
SP1431
EP1434
EPD - 1431-1434
A1 - R. Leveugle,
PY - 2007
KW - RTL dependability evaluation
KW - security validation
KW - fault attacks
KW - fault injection
KW - fault models
VL - 56
JA - IEEE Transactions on Computers
ER -
 
Security often relies on functions implemented in hardware. But various types of attacks have been developed, in particular fault-based attacks allowing a hacker to observe abnormal behaviors, from which secret data can be inferred. Analyzing very early, during a circuit design, the potential impact of faults becomes therefore necessary to avoid security flaws. Dependability analysis environments have been developed to analyze the effect of "natural" faults, for example those induced by particles. This paper discusses the similarities and differences between the two types of application areas, and proposes extensions of the classical fault models to cover security-related constraints. Experimental results on a co-processor for RSA encryption demonstrate the need for such an extended fault model.

[1] A.K. Lenstra, “Memo on RSA Signature Generation in the Presence of Faults,” private communication (available from the author), 28 Sept. 1996.
[2] J. Gracia et al., “Comparison and Application of Different VHDL-Based Fault Injection Techniques,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 233-241, Oct. 2001.
[3] L. Berrojo et al., “New Techniques for Speeding Up Fault-Injection Campaigns,” Proc. Design, Automation and Test in Europe Conf., pp. 847-852, Mar. 2002.
[4] R. Leveugle and K. Hadjiat, “Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments,” J. Electronic Testing: Theory and Applications (JETTA), vol. 19, no. 5, pp. 559-575, Oct. 2003.
[5] D. Alexandrescu, L. Anghel, and M. Nicolaidis, “New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 99-107, Nov. 2002.
[6] K. Hadjiat and R. Leveugle, “Early Dependability Evaluation: Injection of Multiple Bit-Flips,” Proc. Latin Am. Test Workshop, pp. 109-114, 2005.
[7] Y. Monnet et al., “Practical Evaluation of Fault Countermeasures on an Asynchronous DES Cryptoprocessor,” Proc. IEEE Int'l On-Line Testing Symp., pp. 125-130, July 2006.

Index Terms:
RTL dependability evaluation, security validation, fault attacks, fault injection, fault models
Citation:
R. Leveugle, "Early Analysis of Fault-based Attack Effects in Secure Circuits," IEEE Transactions on Computers, vol. 56, no. 10, pp. 1431-1434, July 2007, doi:10.1109/TC.2007.1078
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