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Power-Aware Branch Prediction: Characterization and Design
February 2004 (vol. 53 no. 2) pp. 168-186
Abstract—This paper uses Wattch and the SPEC 2000 integer and floating-point benchmarks to explore the role of branch predictor organization in power/energy/performance trade offs for processor design. Even though the direction predictor by itself represents less than 1 percent of the processor's total power dissipation, prediction accuracy is nevertheless a powerful lever on processor behavior and program execution time. A thorough study of branch predictor organizations shows that, as a general rule, to reduce overall energy consumption in the processor, it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. This not only improves performance, but can also improve the energy-delay product by up to 20 percent. Three techniques, however, can reduce power dissipation without harming accuracy. Banking reduces the portion of the branch predictor that is active at any one time. A new on-chip structure, the prediction probe detector (PPD), uses predecode bits to entirely eliminate unnecessary predictor and branch target buffer (BTB) accesses. Despite the extra power that must be spent accessing it, the PPD reduces local predictor power and energy dissipation by about 31 percent and overall processor power and energy dissipation by 3 percent. These savings can be further improved by using profiling to annotate branches, identifying those that are highly biased and do not require static prediction. Finally, the paper explores the effectiveness of a previously proposed technique, pipeline gating, and finds that, even with adaptive control based on recent predictor accuracy, pipeline gating yields little or no energy savings. [1] D.H. Albonesi, Selective Cache Ways: On-Demand Cache Resource Allocation Proc. 32nd Ann. ACM/IEEE Int'l Symp. Microarchitecture, pp. 248-259, Nov. 1999.
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Index Terms:
Low-power design, energy-aware systems, processor architecture, branch prediction, target prediction, power, banking, highly-biased branches, pipeline gating, speculation control.
Citation:
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea Stan, "Power-Aware Branch Prediction: Characterization and Design," IEEE Transactions on Computers, vol. 53, no. 2, pp. 168-186, Feb. 2004, doi:10.1109/TC.2004.1261827 Usage of this product signifies your acceptance of the Terms of Use.
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