The appearance of floating-point FFT processors and introduction of multiple butterfly units and high-radix structure increase the possibility of read-after-write (RAW) dependency between adjacent stages. The less the transform length is, the more butterfly units are used, the more cycles the butterfly units cost, the more possibility of RAW dependency lurks. In this paper, taking radix-2 time decimation FFT processors for example, we define the minimum slack cycles for each stage, which provides a quantitative method to identify RAW dependencies in FFT processors of variable transform length, and put forward some proposals to reduce or erase RAW dependencies. The minimum slack cycles also indicates the numbers of waiting cycles should be inserted into each stage, which simplifies the design of control path in FFT processors. As to the situation of multiple butterfly units and high-radix structure, same ideas can be used.