Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2007) Design of a High-speed FPGA-based 32-bit Floating-point FFT Processor Haier International Training Center, Qingdao, China July 30-August 01 ISBN: 0-7695-2909-7
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SNPD.2007.46
In this paper, we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor. Usually, limited by long pipeline latency of floating-point operations and multi-port RAM access the throughput of FFT processors can only reach approximately one result per cycle. Through making some improvements on the design of butterfly unit and reorganization of the RAM access, almost a throughput of 2 complex results per cycle can be gotten and twice performance as traditional FFT processors can be achieved. As to a 1024-point FFT transform, it can be finished in (512+10)*10=5220 cycles.
Citation:
Shengmei Mou, Xiaodong Yang, "Design of a High-speed FPGA-based 32-bit Floating-point FFT Processor," snpd, vol. 1, pp.84-87, Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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