Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05) Designing Combinational Circuits with List Homomorphisms Central Michigan University, Mount Pleasant, Michigan August 11-August 13 ISBN: 0-7695-2297-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SERA.2005.35
We present a framework for the unifying high-level synthesis of tree-structured and iterative combinational networks. Based on the theory of list homomorphisms, we develop a standard implementation for tree-structured modules processing the input digits in parallel. The design is systematically specialized to iterative networks processing the input sequentially from the least resp. from the highest significant positions. Throughout the paper, we explicate functional methods for the transformational design of combinational circuits. We illustrate the approach with a parity generatormodule, a comparatormodule, and a priority resolution module.
Index Terms:
High-level synthesis, functional hardware description, list homomorphism, tree network, iterative network, parity generator, comparator, priority resolution
Citation:
Walter Dosch, "Designing Combinational Circuits with List Homomorphisms," sera, pp.288-297, Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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