Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique

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	Similar Articles Articles by Masaya Yoshikawa Articles by Hidekazu Terai

Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05)

Central Michigan University, Mount Pleasant, Michigan

August 11-August 13

ISBN: 0-7695-2297-1

	ASCII Text	x
	Masaya Yoshikawa, Hidekazu Terai, "Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique," Software Engineering Research, Management and Applications, ACIS International Conference on, pp. 130-136, Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05), 2005.

	BibTex	x
	@article{ 10.1109/SERA.2005.23, author = {Masaya Yoshikawa and Hidekazu Terai}, title = {Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique}, journal ={Software Engineering Research, Management and Applications, ACIS International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2297-1}, pages = {130-136}, doi = {http://doi.ieeecomputersociety.org/10.1109/SERA.2005.23}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Software Engineering Research, Management and Applications, ACIS International Conference on TI - Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique SN - 0-7695-2297-1 SP130 EP136 A1 - Masaya Yoshikawa, A1 - Hidekazu Terai, PY - 2005 KW - null VL - 0 JA - Software Engineering Research, Management and Applications, ACIS International Conference on ER -

Masaya Yoshikawa, Ritsumeikan University, Japan

Hidekazu Terai, Ritsumeikan University, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SERA.2005.23

Deep-Sub-Micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestiondriven placement technique based on asynchronous parallel Genetic Algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.

Citation:

Masaya Yoshikawa, Hidekazu Terai, "Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique," sera, pp.130-136, Third ACIS Int'l Conference on Software Engineering Research, Management and Applications (SERA'05), 2005

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