In this paper we address the "rate analysis" problem for media-processing pla$brnzs consisting oJ'rnultiple processor cores connected zn a pipelined fashion. More precisely, we aim at determining tight bounds on the rates at which multimedia streams can be fed into such urchitectures. These bounds depend on urchitectuml constt-uints (e.g. the available on-chip memory, bus urhitrution policies, etc.), as well as the upplicution churacteristics (e.g. application partitioning und mapping, workloud rutes generaled by different tasks, etc.). The proposed frurnework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architrctural parameters, mapping of the application, or chunging the QoS requirements associated with the input strrarns.