11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05) Efficient Integration of Bimodal Branch Prediction and Pipeline Analysis Hong Kong, China August 17-August 19 ISBN: 0-7695-2346-3
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/RTCSA.2005.41
Advanced microarchitectural features such as caches and branch prediction mechanisms supporting speculative execution are becoming commonplace within modern microprocessors. For developers of real-time systems, these mechanisms present predictability problems. Previous work has demonstrated accurate analysis for instruction caches, data caches, and branch prediction mechanisms is possible. However, the integration of these individual analysis methods is difficult to do without large increases in computational complexity or the introduction of pessimism regarding the Worst-Case Execution Time (WCET) estimate. In this paper, we discuss how a previously published analysis method for branch predictors can be integrated with instruction pipeline analysis.
Citation:
Iain Bate, Ralf Reutemann, "Efficient Integration of Bimodal Branch Prediction and Pipeline Analysis," rtcsa, pp.39-44, 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||