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Third International Workshop on Real-Time Computing Systems Application (RTCSA'96)
Static scheduling of hard real-time code with instruction-level timing accuracy
Seoul, Korea
October 30-November 01
ISBN: 0-8186-7626-4
T.M. Chung, Sung Kyun Kwan Univ., Suwon, South Korea
H.G. Dietz, Sung Kyun Kwan Univ., Suwon, South Korea
In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level compiler code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.
Index Terms:
processor scheduling; real-time systems; timing fault; instruction-level timing accuracy; high-level language code; instruction-level; compiler code scheduling; timing analysis; genetic search algorithm; search space
Citation:
T.M. Chung, H.G. Dietz, "Static scheduling of hard real-time code with instruction-level timing accuracy," rtcsa, pp.203, Third International Workshop on Real-Time Computing Systems Application (RTCSA'96), 1996
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