12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06) A Performance Estimation Tool for Video Applications San Jose, California April 04-April 07 ISBN: 0-7695-2516-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/RTAS.2006.6
A trend in the consumer electronics market is the demand for new applications that have a lot of similarities to older applications but the new ones impose more challenging and special-purpose performance requirements. In the digital signal processing (DSP) industry, this clearly reflects a transition from the design regime of general DSP to the application-specific DSP. A key in effecting this transition is the engineering capability to make the design specification "match" the application, before detailed design starts. In this paper, we present an effective simulation tool to assist in the generation of accurate design specifications. It models the application by a parameter-driven conditional data-flow graph (CDFG) and the hardware (HW) architecture by a configurable HW graph. The simulator takes the application CDFG and HW graph as the input and carries the simulation at a low level to catch the detailed HW activities. Experimental results show that our tool is not only able to accurately estimate system performance, but also helps to identify performance bottlenecks and to find the optimal software (SW) implementation solution for video applications.
Citation:
Zhengting He, Cheng Peng, Aloysius Mok, "A Performance Estimation Tool for Video Applications," rtas, pp.267-276, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||