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12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06)
Uniprocessor Scheduling Under Precedence Constraints
San Jose, California
April 04-April 07
ISBN: 0-7695-2516-4
L. Mangeruca, PARADES E.E.I.G., Italy
A. Ferrari, PARADES E.E.I.G., Italy
A.L. Sangiovanni-Vincentelli, University of California at Berkeley
In this paper we present a novel approach to the constrained scheduling problem, while addressing a more general class of constraints that arise from the timing requirements on real-time embedded controllers and from the implementation of mixed data-flow/event-driven real-time systems. We provide general necessary and sufficient conditions for scheduling under precedence constraints and derive sufficient conditions for two well-known scheduling policies. We define mathematical problems that provide optimum priority and deadline assignments, while ensuring both precedence constraints and system?s schedulability.We show how these problems can be relaxed to corresponding ILP formulations leveraging on available solvers.
Citation:
L. Mangeruca, A. Ferrari, A.L. Sangiovanni-Vincentelli, "Uniprocessor Scheduling Under Precedence Constraints," rtas, pp.157-166, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), 2006
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