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18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07)
FPGA Prototyping Strategy for a H.264/AVC Video Decoder
Porto Alegre, RS, Brazil
May 28-May 30
ISBN: 0-7695-2834-1
ASCII Text
x 
 
Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano V. Agostini, Sergio Bampi, Altamiro A. Susin, "FPGA Prototyping Strategy for a H.264/AVC Video Decoder," Rapid System Prototyping, IEEE International Workshop on, pp. 174-180, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007.
 
 
BibTex
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@article{ 10.1109/RSP.2007.23,
author = {Vagner S. Rosa and Wagston T. Staehler and Arnaldo Azevedo and Bruno Zatt and Roger E. Porto and Luciano V. Agostini and Sergio Bampi and Altamiro A. Susin},
title = {FPGA Prototyping Strategy for a H.264/AVC Video Decoder},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {2007},
issn = {1074-6005},
pages = {174-180},
doi = {http://doi.ieeecomputersociety.org/10.1109/RSP.2007.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - FPGA Prototyping Strategy for a H.264/AVC Video Decoder
SN - 1074-6005
SP174
EP180
A1 - Vagner S. Rosa,
A1 - Wagston T. Staehler,
A1 - Arnaldo Azevedo,
A1 - Bruno Zatt,
A1 - Roger E. Porto,
A1 - Luciano V. Agostini,
A1 - Sergio Bampi,
A1 - Altamiro A. Susin,
PY - 2007
KW - null
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
Vagner S. Rosa, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Wagston T. Staehler, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Arnaldo Azevedo, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Bruno Zatt, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Roger E. Porto, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Luciano V. Agostini, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Sergio Bampi, Univ. Fed. Rio Grande do Sul Porto Alegre, RS, Brazil
Altamiro A. Susin, Universidade Fed. de Pelotas Pelotas, RS, Brazil
This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post place-and-route synthesis results indicate that the designed architectures are able to target real time when processing HDTV 1080p frames (1080x1920). The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The prototyping strategy used an embedded Power PC and associated logic and buffering to control the modules under prototyping. A host computer, running the reference software, was used to generate the input stimuli and to compare the results, through a RS-232 serial interface.
Citation:
Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano V. Agostini, Sergio Bampi, Altamiro A. Susin, "FPGA Prototyping Strategy for a H.264/AVC Video Decoder," rsp, pp.174-180, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007
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