Virtual Machine technology allows for the reuse of applications and code over various heterogeneous platforms. A virtual machine simply adds another layer of abstraction between the application and the native hardware. A major drawback of an application running on a virtual machine, however, is that the performance is below that of an application targeted for a native platform. Previous work has dealt with improving the performance of a virtual machine through hardware support using field programmable gate arrays (FPGAs). With the growing capacities of FPGAs it is becoming possible to provide higher levels of hardware support. This work examines the Java Virtual Machine (JVM), by implementing it in hardware, using a Network-on-Chip (NoC) design methodology. A subset of the JVM instructions are implemented in a hardware engine, with the more complex operations performed in software, and this hardware engine is replicated numerous times within the FPGA. By having several JVM instances execute in hardware concurrently, multiple applications and/or threads can simultaneously benefit from hardware implementation.