In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology and a supporting tool results in inefficient partitioning. In this paper, we present novel algorithms for clock period estimation and estimation of upper bound on execution time under given resource constraints which includes constraints on number of ports in the register file and memory. Experimental results on benchmarks from the High-Level Synthesis (HLS) [1], MiBench [2] and Mediabench [3] suites, show the effectiveness of our algorithms.