This paper presents a heterogeneous model of an Optical Network-on Chip (ONoC). An ONoC is an optical interconnect architecture integrated on a System-on-Chip, and is intended to replace traditional electrical Networks-on- Chip (NoC) to overcome their future bandwidth limitations. To evaluate the advantages of a technological implementation of an ONoC, it is necessary to model its behavior and to realize a virtual prototype to estimate its power, latency, area, bandwidth, and subsequently to compare these parameters with the performance of a classical NoC. To model the ONoC at a high abstraction level, a rich system-level design language is used (SystemC). A bottom-up approach is used for the high level ONoC model description, and the performance values used at this level are extracted from the physical level with specific tools and models.