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Third International Conference on the Quantitative Evaluation of Systems - (QEST'06)
Riverside, California
September 11-September 14
ISBN: 0-7695-2665-9
Matthew Curtis-Maury, Virginia Tech
Christos D. Antonopoulos, College of William and Mary
Performance monitoring counters (PMCs) are registers within a processor which can be programmed to count the occurrences of particular processor events, such as L2 cache misses, stall cycles, etc. Due to the insight that they provide into the execution of an application on a given architecture, hardware performance counters are seeing increasing popularity in both the research [1] and industrial communities [3].
Citation:
Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Christos D. Antonopoulos, "PACMAN: A PerformAnce Counters MANager for Intel Hyperthreaded Processors," qest, pp.141-144, Third International Conference on the Quantitative Evaluation of Systems - (QEST'06), 2006
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