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Second International Conference on the Quantitative Evaluation of Systems (QEST'05)
Performance Modeling and Architecture Exploration of Network Processors
Torino, Italy
September 19-September 22
ISBN: 0-7695-2427-3
ASCII Text
x 
 
S. Govind, R. Govindarajan, "Performance Modeling and Architecture Exploration of Network Processors," Quantitative Evaluation of Systems, International Conference on, pp. 189-198, Second International Conference on the Quantitative Evaluation of Systems (QEST'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/QEST.2005.29,
author = {S. Govind and R. Govindarajan},
title = {Performance Modeling and Architecture Exploration of Network Processors},
journal ={Quantitative Evaluation of Systems, International Conference on},
volume = {0},
year = {2005},
isbn = {0-7695-2427-3},
pages = {189-198},
doi = {http://doi.ieeecomputersociety.org/10.1109/QEST.2005.29},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quantitative Evaluation of Systems, International Conference on
TI - Performance Modeling and Architecture Exploration of Network Processors
SN - 0-7695-2427-3
SP189
EP198
A1 - S. Govind,
A1 - R. Govindarajan,
PY - 2005
KW - null
VL - 0
JA - Quantitative Evaluation of Systems, International Conference on
ER -
 
S. Govind, Indian Institute of Science Bangalore, India
R. Govindarajan, Indian Institute of Science Bangalore, India

This paper proposes a Petri net model for a commercial network processor (Intel IXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, Network Address Translation, and IP Security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations.

We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.

Citation:
S. Govind, R. Govindarajan, "Performance Modeling and Architecture Exploration of Network Processors," qest, pp.189-198, Second International Conference on the Quantitative Evaluation of Systems (QEST'05), 2005
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