Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions. In this paper, we model the sensitivity of individual circuit classes to Single Event Upsets using predictive technology models over a range of CMOS device sizes from 90nm down to 32nm. Modeling the relative position of particle strikes as injected current pulses of varying amplitude and fall time, we find that the critical charge for each technology is an almost linear function both of the fall time of the injected current and the supply voltage. This simple relationship will simplify the task of estimating circuit-level Soft Error Rate (SER) and support the development of an efficient SER modeling and optimization tool that might eventually be integrated into a high level language design flow.