Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%.