Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature

P
PRDC
2001
Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01)
Abstract - Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature

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Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01)

Seoul, Korea

December 17-December 19

ISBN: 0-7695-1414-6

	ASCII Text	x
	Sei Takahashi, Munehisa Taira, Hidetaka Saegusa, Takehiko Hoshino, Hideo Nakamura, "Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature," Pacific Rim International Symposium on Dependable Computing, IEEE, pp. 191, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001.

	BibTex	x
	@article{ 10.1109/PRDC.2001.992697, author = {Sei Takahashi and Munehisa Taira and Hidetaka Saegusa and Takehiko Hoshino and Hideo Nakamura}, title = {Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature}, journal ={Pacific Rim International Symposium on Dependable Computing, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1414-6}, pages = {191}, doi = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2001.992697}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Pacific Rim International Symposium on Dependable Computing, IEEE TI - Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature SN - 0-7695-1414-6 SP EP A1 - Sei Takahashi, A1 - Munehisa Taira, A1 - Hidetaka Saegusa, A1 - Takehiko Hoshino, A1 - Hideo Nakamura, PY - 2001 VL - 0 JA - Pacific Rim International Symposium on Dependable Computing, IEEE ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2001.992697

A bus-level synchronized computer system is widely Utilized in the field of railway signaling of Japan. It may Be recognized that there is a problem of disadvantage in a manufacturing cost reduction. We intend to integrate a bus-level synchronized FS computer into an LSI chip in expectation of cost reduction and performance enhancement. An economical FS one-chip computer by utilizing system LSI technology is realized. It assures fail-safety by means of new fault diagnosis mechanism depending on an M-sequence code signature. In this paper, these contents and techniques are reported in detail.

Citation:

Sei Takahashi, Munehisa Taira, Hidetaka Saegusa, Takehiko Hoshino, Hideo Nakamura, "Development of a Fail-Safe Microprocessor LSI with Self-Diagnosis Mechanism Depending on an M-Sequence Code Signature," prdc, pp.191, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001

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