A Novel Fault Tolerant Approach for SRAM-Based FPGAs

P
PRDC
1999
Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99)
Abstract - A Novel Fault Tolerant Approach for SRAM-Based FPGAs

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Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99)

Hong Kong, China

December 16-December 17

ISBN: 0-7695-0371-3

	ASCII Text	x
	Jian Xu, Paifa Si, Weikang Huang, Fabrizio Lombardi, "A Novel Fault Tolerant Approach for SRAM-Based FPGAs," Pacific Rim International Symposium on Dependable Computing, IEEE, pp. 40, Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99), 1999.

	BibTex	x
	@article{ 10.1109/PRDC.1999.816210, author = {Jian Xu and Paifa Si and Weikang Huang and Fabrizio Lombardi}, title = {A Novel Fault Tolerant Approach for SRAM-Based FPGAs}, journal ={Pacific Rim International Symposium on Dependable Computing, IEEE}, volume = {0}, year = {1999}, isbn = {0-7695-0371-3}, pages = {40}, doi = {http://doi.ieeecomputersociety.org/10.1109/PRDC.1999.816210}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Pacific Rim International Symposium on Dependable Computing, IEEE TI - A Novel Fault Tolerant Approach for SRAM-Based FPGAs SN - 0-7695-0371-3 SP EP A1 - Jian Xu, A1 - Paifa Si, A1 - Weikang Huang, A1 - Fabrizio Lombardi, PY - 1999 KW - FPGA KW - fault-tolerant routing KW - fault-tolerant architecture VL - 0 JA - Pacific Rim International Symposium on Dependable Computing, IEEE ER -

Jian Xu, Fudan University

Paifa Si, Fudan University

Weikang Huang, Fudan University

Fabrizio Lombardi, Texas A&M University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.1999.816210

This paper presents a novel fault tolerant approach for SRAM-Based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. Fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature[1, 4].

Index Terms:

FPGA, fault-tolerant routing, fault-tolerant architecture

Citation:

Jian Xu, Paifa Si, Weikang Huang, Fabrizio Lombardi, "A Novel Fault Tolerant Approach for SRAM-Based FPGAs," prdc, pp.40, Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99), 1999

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