Nowadays, the commercial processors are designed on superscalar architectures. These processors use branch prediction techniques to forecast the code path that will be followed after each branch instruction, but before its execution. Branch prediction avoids pipeline stalls, anticipating the execution of instructions and providing high instruction level parallelism. This work evaluates a recent approach for intelligent branch prediction that is based on neural networks. Multiple Perceptrons were organized in a two-level prediction table indexed by the branch address in the first level and by the branch history pattern in the second level. Many situations were examined changing the number of lines and the associativity of the prediction table. This approach showed ability to predict branches, reaching more than 98% in some cases.