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Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06)
Designing Reliable Architecture for Stateful Fault Tolerance
Taipei, Taiwan
December 04-December 07
ISBN: 0-7695-2736-1
Indranil Saha, Honeywell Technology Solutions Lab Pvt. Ltd., India
Debapriyay Mukhopadhyay, Honeywell Technology Solutions Lab Pvt. Ltdl, India
Satyajit Banerjee, Honeywell Technology Solutions Lab Pvt. Ltd., India
Performance and fault tolerance are two major issues that need to be addressed while designing highly available and reliable systems. The network topology or the notion of connectedness among the network nodes defines the system communication architecture and is an important design consideration for fault tolerant systems. A number of fault tolerant designs for specific multi-processor architecture exists in the literature, but none of them discriminates between stateless and stateful failover.

In this paper, we propose a reliable network topology and a high availability framework which is tolerant upto a maximum of k node faults in a network and is designed specifically to meet the needs of stateful failover. Assuming the nodes in the network are capable of handling multiple processes, through our design we have been able to prove that in the event of k node failures the load can be uniformly distributed across the network - ensuring load balance. We also provide an useful characterization for the network, which under the proposed framework ensures one hop communication between the required nodes.

Index Terms:
Stateful Failover, k-Fault Tolerance, Network Topology, Harary Graph, Load Balance.
Citation:
Indranil Saha, Debapriyay Mukhopadhyay, Satyajit Banerjee, "Designing Reliable Architecture for Stateful Fault Tolerance," pdcat, pp.545-551, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006
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