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Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06)
Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy
Taipei, Taiwan
December 04-December 07
ISBN: 0-7695-2736-1
Caixia Sun, National University of Defense Technology, China
Hongwei Tang, National University of Defense Technology, China
Minxuan Zhang, National University of Defense Technology, China
In Simultaneous Multithreading (SMT) processors, the instruction fetch policy affects the speed at which each thread runs and overall throughput. However, current fetch policies almost focus on overall throughput optimization, and provide no control over how fast individual threads run. As a result, the performance of a thread varies with fetch policy and the workload it is executed. This performance unpredictability means that the execution time of a thread is unpredictable. So only depending on the Operating System (OS) thread scheduler to guarantee the execution time constraint of a time critical thread is not enough even fails. The hardware must ensure that the performance of the time critical thread is predictable in any timeslice.

In this paper, we propose a novel fetch policy to control performance of a time critical thread in SMT processors. We evaluate our policy using many different workloads, and results show that for more than 94% of all cases measured, our policy can achieve the desired performance. For the failing cases, the average variance is within 1.25%. Furthermore, our policy does not sacrifice overall throughput severely. Compared to fetch policies orienting towards throughput maximization such as ICOUNT, the average degradation of overall throughput is less than 3%. Especially, out policy makes efforts to maximize the throughput of all co-scheduled threads other than the time critical one, and gives 98.25% of the throughput achieved by ICOUNT on average.

Citation:
Caixia Sun, Hongwei Tang, Minxuan Zhang, "Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy," pdcat, pp.217-222, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006
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