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Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05)
On-chip Debug for an Asynchronous Java Accelerator
Dalian, China
December 05-December 08
ISBN: 0-7695-2405-2
ASCII Text
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Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere, "On-chip Debug for an Asynchronous Java Accelerator," Parallel and Distributed Computing Applications and Technologies, International Conference on, pp. 312-315, Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05), 2005.
 
 
BibTex
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@article{ 10.1109/PDCAT.2005.175,
author = {Zheng Liang and Juha Plosila and Lu Yan and Kaisa Sere},
title = {On-chip Debug for an Asynchronous Java Accelerator},
journal ={Parallel and Distributed Computing Applications and Technologies, International Conference on},
volume = {0},
year = {2005},
isbn = {0-7695-2405-2},
pages = {312-315},
doi = {http://doi.ieeecomputersociety.org/10.1109/PDCAT.2005.175},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel and Distributed Computing Applications and Technologies, International Conference on
TI - On-chip Debug for an Asynchronous Java Accelerator
SN - 0-7695-2405-2
SP312
EP315
A1 - Zheng Liang,
A1 - Juha Plosila,
A1 - Lu Yan,
A1 - Kaisa Sere,
PY - 2005
KW - Embedded
KW - Co-design
KW - Debug
KW - Java
KW - Asynchronous
VL - 0
JA - Parallel and Distributed Computing Applications and Technologies, International Conference on
ER -
 
Zheng Liang, Dept. of Computer Science, Abo Akademi University
Juha Plosila, Dept. of Information Technology, University of Turku, Finland
Lu Yan, Dept. of Computer Science, Abo Akademi University
Kaisa Sere, Dept. of Computer Science, Abo Akademi University
The solution to debug a problem in a deeply embedded system is to integrate the debug and communication module inside the chip. In this paper, we propose an on-chip in-circuit emulation (ICE) architecture for debugging an asynchronous Java accelerator core which can be integrated with any existing processor and operating system. The operation of this ICE module and the debug strategy of the Java accelerator are specifically designed for asynchronous implementation. They not only facilitate the system development but also provide a manufacture test method for asynchronous chips.
Index Terms:
Embedded, Co-design, Debug, Java,Asynchronous
Citation:
Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere, "On-chip Debug for an Asynchronous Java Accelerator," pdcat, pp.312-315, Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05), 2005
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