In this paper a new partitioning algorithm for parallelization of post-placement VLSI procedures is presented. The partitioning technique divides problem tasks into multiple sessions of parallel processes, so that interprocessor communication is entirely removed during each session. Communication is performed only in the end of each session. The algorithm is especially useful for parallelizing processes whose tasks are heavily connected to each other and may result in high communication overhead in parallel processing. Post-placement optimization of electrical violations represents such a task and was implemented in our experiments to validate the partitioning and parallelization techniques. On industry ASIC designs ranging in size from 300K to 1M gates, our partitioning scheme speeds up the execution time of this optimization by up to 2.5x over serial processing by dynamically utilizing 1-6 processors.