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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture
Dresden, Germany
September 07-September 10
ISBN: 0-7695-2080-4
ASCII Text
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Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov, "Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture," Parallel Computing in Electrical Engineering, International Conference on, pp. 165-170, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.
 
 
BibTex
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@article{ 10.1109/PCEE.2004.60,
author = {Lev Kirischian and Irina Terterian and Pil Woo Chun and Vadim Geurkov},
title = {Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2004},
isbn = {0-7695-2080-4},
pages = {165-170},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.60},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture
SN - 0-7695-2080-4
SP165
EP170
A1 - Lev Kirischian,
A1 - Irina Terterian,
A1 - Pil Woo Chun,
A1 - Vadim Geurkov,
PY - 2004
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Lev Kirischian, Ryerson University Toronto, Canada
Irina Terterian, Ryerson University Toronto, Canada
Pil Woo Chun, Ryerson University Toronto, Canada
Vadim Geurkov, Ryerson University Toronto, Canada
In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro-architectures when hardware fault occurs. This Paper presents a description of system level architecture of run-time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.
Citation:
Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov, "Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture," parelec, pp.165-170, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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