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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Dynamically Reconfigurable Hardware for Object-Oriented Processing
Dresden, Germany
September 07-September 10
ISBN: 0-7695-2080-4
ASCII Text
x 
 
Andreas K?, Sorin A. Huss, "Dynamically Reconfigurable Hardware for Object-Oriented Processing," Parallel Computing in Electrical Engineering, International Conference on, pp. 181-186, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/PCEE.2004.30,
author = {Andreas K? and Sorin A. Huss},
title = {Dynamically Reconfigurable Hardware for Object-Oriented Processing},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2004},
isbn = {0-7695-2080-4},
pages = {181-186},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.30},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Dynamically Reconfigurable Hardware for Object-Oriented Processing
SN - 0-7695-2080-4
SP181
EP186
A1 - Andreas K?,
A1 - Sorin A. Huss,
PY - 2004
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Andreas K?, Darmstadt University of Technology
Sorin A. Huss, Darmstadt University of Technology
The focus of this paper is to establish a link of dynamic structures as found in software-based systems function descriptions to hardware implementations. Specific properties of object-oriented software methodologies and partially reconfigurable FPGAs are first analyzed. Then, both a reconfigurable processing unit and an approach how to map object classes to such execution units are elaborated. The feasibility of the proposed mapping method is demonstrated for some application examples.
Citation:
Andreas K?, Sorin A. Huss, "Dynamically Reconfigurable Hardware for Object-Oriented Processing," parelec, pp.181-186, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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