International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04) An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures Dresden, Germany September 07-September 10 ISBN: 0-7695-2080-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.13
This document presents a theoretical analysis of state-of-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficient method of hardware threading in certain scenarios.The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.
Citation:
Tomasz Madajczak, "An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures," parelec, pp.71-76, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||