An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation

P
PARELEC
2004
International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Abstract - An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation

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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)

Dresden, Germany

September 07-September 10

ISBN: 0-7695-2080-4

	ASCII Text	x
	Daniel Matolin, J? Schreiter, Stefan Getzlaff, Ren? Sch?, "An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation," Parallel Computing in Electrical Engineering, International Conference on, pp. 51-55, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.

	BibTex	x
	@article{ 10.1109/PCEE.2004.11, author = {Daniel Matolin and J? Schreiter and Stefan Getzlaff and Ren? Sch?}, title = {An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2004}, isbn = {0-7695-2080-4}, pages = {51-55}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation SN - 0-7695-2080-4 SP51 EP55 A1 - Daniel Matolin, A1 - J? Schreiter, A1 - Stefan Getzlaff, A1 - Ren? Sch?, PY - 2004 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Daniel Matolin, Dresden University of Technology, Germany

J? Schreiter, Dresden University of Technology, Germany

Stefan Getzlaff, Dresden University of Technology, Germany

Ren? Sch?, Dresden University of Technology, Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.11

We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.

Citation:

Daniel Matolin, J? Schreiter, Stefan Getzlaff, Ren? Sch?, "An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation," parelec, pp.51-55, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004

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