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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
Dresden, Germany
September 07-September 10
ISBN: 0-7695-2080-4
ASCII Text
x 
 
Sebastian Siegel, Renate Merker, "Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays," Parallel Computing in Electrical Engineering, International Conference on, pp. 85-90, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/PCEE.2004.10,
author = {Sebastian Siegel and Renate Merker},
title = {Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2004},
isbn = {0-7695-2080-4},
pages = {85-90},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
SN - 0-7695-2080-4
SP85
EP90
A1 - Sebastian Siegel,
A1 - Renate Merker,
PY - 2004
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Sebastian Siegel, Dresden University of Technology, Germany
Renate Merker, Dresden University of Technology, Germany
This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.
Citation:
Sebastian Siegel, Renate Merker, "Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays," parelec, pp.85-90, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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